The present invention relates generally to circuits for electrostatic discharge (“ESD”) protection.
A semiconductor integrated circuit (“IC”) is generally susceptible to an electrostatic discharge (“ESD”) event, which may damage or destroy the IC. An ESD event refers to a phenomenon of electrical discharge of a current (positive or negative) for a short duration during which a large amount of current is provided to the IC. The susceptibility of a device to ESD can be determined by testing for one of three models: Human Body Model (“HBM”), Machines Model (“MM”), and Charged-Device Model (“CDM”).
The ESD Association Standard for the Development of an Electrostatic Discharge Control Program for Protection of Electrical and Electronic Parts, Assemblies and Equipment (Excluding Electrically Initiated Explosive Device), ANSI/ESD-S20.20-1999 (Aug. 4, 1999), provides for ESD sensitivity testings for each of the three models. The HBM model represents the discharge from the fingertip of a standing individual delivered to conductive leads of a device. In an HBM model ESD test circuit modeled by a 100 picofarad (pF) capacitor, representing the effective capacitance of the human body, a discharge through a switching component and 1,500 ohm series resistor, representing the effective resistance of the human body, into the device under tests is a double exponential waveform with a rise time of 2-10 nanoseconds (nS) and a pulse duration of approximately 150 nS.
The MM model represents a rapid discharge from items such as a charged board assembly, charged cables, or the conduction arm of an automatic tester. The effective capacitance is approximately 200 pF discharged through a 500 nanohenry (nH) inductor directly into the device because the effective resistance of the machine is approximately zero. The discharge is a sinusoidal decaying waveform having a peak current of approximately 3.8 amperes (A) with a resonant frequency of approximately 16 MHz.
The CDM model represents a phenomenon where a device acquires a charge through frictional or electrostatic induction processes and then abruptly touches a grounded object or surface. FIG. 1 is a schematic diagram illustrating the CDM phenomenon. Referring to FIG. 1, most of the charge is accumulated in a substrate, including a base, a bulk or a well of the device, and is uniformly distributed in the substrate. Unlike the HBM model and the MM model, the CDM model includes situations where the device itself becomes charged and discharges to ground. The rise time is generally less than 200 picoseconds (pS), and the entire ESD event can take place in less than 2 nS. Current levels can reach several tens of amperes during discharge, which are remarkably greater than those of the HBM and MM models.
Since the charge is mainly stored in the substrate, a gate oxide of an input-stage metal-oxide-semiconductor (“MOS”) transistor may be easily damaged by a CDM ESD. FIG. 2 is a schematic circuit diagram of a conventional ESD protection circuit for an input-stage inverter. Referring to FIG. 2, the ESD protection circuit comprises an ESD clamp and an n-type metal-oxide-semiconductor (“NMOS”) transistor Mn1, and the input-stage inverter comprises a p-type metal-oxide-semiconductor (“PMOS”) transistor Mp5 and an NMOS transistor Mn5. The ESD protection circuit designed for HBM and MM ESD protection, however, may not provide effective CDM ESD protection for the input-stage inverter. When a CDM ESD occurs as an input pad is grounded, a CDM ESD current IESD due to negative charge may damage the gate oxide of the NMOS transistor Mn5. Likewise, a CDM ESD current due to positive charge stored in the substrate may also damage the gate oxide of the NMOS transistor Mn5.
Verious Studies have addressed protecting an IC from ESD events. In a paper entitled “Active-source-pump (ASP) technique for ESD design window expansion and ultra-thin gate oxide protection in sub-90 nm Technologies” by Mergens et al., Proc. of IEEE CICC, 2004, pp. 251-254, it has been found that gate-to-source breakdown voltages are much lower than gate-to-bulk breakdown voltages. Consequently, pumping schemes to reduce a gate-to-source voltage so as to prevent the gate oxide from CDM ESD damage have been proposed to enhance the ESD robustness in nanoscale complementary metal-oxide-semiconductor (“CMOS”) techniques.